Published: 2015, Feb 5. Updated: 2019, October 5.
This is chapter 3 of the DRSSTC design guide: IGBTs
Choosing a switch for a Tesla coil inverter is not a simple task if one looks into all the parameters given in a datasheet, and even more complex if you run the numbers through a IGBT inverter design application note from almost any manufacturer.
All datasheet values are given for a specific gate voltage, collector-emitter voltage, current, duty cycle, temperatures etc. They are based on hard switching currents into either a resistive or inductive load, especially those datasheets with resistive loads can seem faster than they would in a inductive application. Tesla coils like the DRSSTC rely on soft switching, for which there is little to no data in datasheets, but generally that means switch times are faster, losses lower and currents switched can be higher.
How to drive a IGBT in the best possible way and maintain what is called “Switch fast as slowly as possible” will be covered in chapter 7: GDT / driver.
How to read a IGBT datasheet 
Maximum Gate-to-Emitter Voltage (VGE)
The gate voltage is limited by the thickness and characteristics of the gate oxide layer. Though the gate dielectric rupture is typically around 80 volts, the user is normally limited to 20 or 30V to limit current under fault conditions and to ensure long term reliability.
It is normal practice to drive IGBTs at +24VDC with the Steve Ward universal driver and clones of it that most use. The reason for the gate voltage limit is not so much for protecting the gate itself, it will first break down at some 80 Volt. Higher gate voltage means higher currents can be conducted through the Collector-Emitter. We take advantage of this by pushing the gate a little over its rated voltage to allow us to conduct higher currents through the IGBT, at the cost of higher switching losses. As explained by manufacturers in the following.
It is important to note however that IGBTs exhibit relatively high gain even at high gate-emitter voltage. This is because increasing the flow of electrons by increasing the gate-emitter voltage also increases the flow of holes. The gain of a high voltage power MOSFET however is very insensitive to gate voltage once fully on.
VCE(SAT) – Collector-Emitter On/Saturation Voltage
This is the collector-emitter voltage across the IGBT at a specified collector current, gate-emitter voltage, and junction temperature. Since VCE(sat) is temperature dependent, it is specified both at room temperature and hot.
From these graphs, a circuit designer can estimate conduction loss and the temperature coefficient of VCE(sat). Conduction power loss is VCE(sat) times collector current.
It is important to find a IGBT with as low a VCE(SAT) rating as possible. The conduction losses across the IGBT scales linearly with the VCE(SAT) voltage.
Collector-Emitter saturation voltage lowers dramatically at gate voltages above 12 Volt Gate-Emitter voltage, which is why a IGBT should never be driven with less than 15 Volt. Above 20 Volt the Collector-Emitter saturation voltage does not decline that much, but it is still lessened with higher gate voltage.
VCES – Collector-Emitter Voltage
This is a rating of the maximum voltage between the collector and emitter terminals with the gate shorted to the emitter. This is a maximum rating, and depending on temperature, the maximum permissible collector-emitter voltage could actually be less than the VCES rating. See the description of BVCES in Static Electrical Characteristics.
The most useful IGBTs for DRSSTCs are those with a voltage rating of 600 V and 1200 V as they provide the switching speed and high current ratings that fall within the region of DRSSTCs. Higher break down voltages normally mean slower switching times. Higher voltage would make it much more expensive to construct a MMC / tank capacitor to handle the higher voltage at high currents.
Since we switch much higher currents in a DRSSTC by soft switching, than the rated pulse currents for hard switching, we can not go by the normal 80% of VCES derating for the supply voltage. There will be a risk of voltage spikes punching through the IGBT. For the matter of using them in a DRSSTC, the derating should be 66% of VCES.
BVCES – Collector-Emitter Breakdown Voltage
BVCES has a positive temperature coefficient. At a fixed leakage current, an IGBT can block more voltage when hot than when cold. In fact, when cold, the BVCES specification is less than the VCES rating. At -50 ºC junction temperature, BVCES is about 93% of the nominal 25 ºC specification and at 150 ºC, BVCES is about 110%
This would correspond to a 1200V IGBT can only block 1116 V at its lowest temperature rating and 1320 V at its highest. So as far as voltage rating goes, it is better to have a IGBT running warm compared to trying to cool it with peltier elements or liquid nitrogen.
The switch times given in a IGBT datasheet is defined within the limits of the four bulletins below. So in reality switch times can be longer, losses bigger and small amounts of cross conduction can occur. The switch times are normally given for hard switching and are thus much slower than what we see in DRSSTC use.
- Turn-on delay time: 10% of gate voltage to 10% of collector current
- Rise time: 10% to 90% of collector current
- Turn-off delay time: 90% of gate voltage to 10% of collector voltage
- Fall time: 90% to 10% of collector current.
Switching times provide a useful guideline to establish the appropriate dead-time between the turn-off and subsequent turn-on of complementary devices in a half bridge configuration and the minimum and maximum pulse widths. They provide a very unreliable indication of switching losses. Because of the current tail, a significant part of the turn-off energy may be dissipated at a current that is below 10% of the load current. The voltage fall time, on the other hand, is not characterized in any way. Thus, two significant contributors to losses are not properly accounted for by the switching times.
It is important to see if the manufacturer follows the unwritten standard or they write the datasheets in their own words. Fuji is known to include Trise times in the Ton time and Tfall times in the Toff times, this makes the IGBT look slower when comparing with others if attention is not given, but all times just added together.
What is the linear region
The linear region is often mentioned when switching losses are discussed or if someone ask “Is this IGBT fast enough for a DRSSTC?” at this particular frequency. I will try to explain the physical mechanism inside the IGBT when it turns on and off, the time period we call the linear region.
The minority carriers in the N- layer, i.e., the base of the PNP part, have to be injected at turn-on and collected at turn-off. This slows down the switching speed of the IGBT.
These minority carriers stored cause the characteristic “tail” in the current waveform of an IGBT at turn-off.
As the MOSFET channel stops conducting, electron current ceases and the IGBT current drops rapidly to the level of the hole recombination current at the beginning of the tail. The tail is important mainly because it increases switching losses, as tail current flows when the voltage across the IGBT is at its highest level.
In resonant / soft switching the turn on losses are primarily given by the parasitic inductance of the IGBT package itself. The turn off loss is very low because the resonant current has significantly decreased by the time we give the off signal to the IGBT. So there are much less holes to recombine in soft switching than hard switching, this is why it can be switched on and off much faster.
Soft switching and zero current switching 
As described above the IGBT can be switched on and off faster due to the declining current of the resonant load, we do not have to switch off the current, but we switch when the current is as low as possible.
Only some serious semiconductor physics simulations can tell us how much faster they can switch. The following curves show the difference in switching losses from hard switching to soft switching.
A CM600 that can switch on in a mere 100 ns for both on and off is about 10 times faster than its hard switching specifications from the datasheet. This switch speed reduction can not be assumed to be linear across all sizes of IGBTs and there exists newer die technologies where the junction is optimized for soft switching, whereas most older IGBTs are all optimized for hard switching. Anywhere between 2 to 10 times as fast could be used to extrapolate the switching speeds from the datasheet. This guide will for the following examples assume 4 times faster switch speeds. These oscilloscope shots of a CM600 switching in a large DRSSTC with a phase lead driver were kindly provided by Kizmo. Here the aforementioned very fast switching can be seen in reality.
Zero current switching (ZCS) is only true for a lossless circuit with perfect switches, it is only a term that in the real world should be called “as close to zero current switching as possible”.
To avoid anti-parallel diode losses and cross conduction losses we have to finish switching the current off before passing zero, else the current continues into the negative domain where the other switch/switches would turn on.
With higher frequency the angle of the current is also steeper and thus we have to switch off larger currents as frequency goes up, this is also a reason why larger Tesla coils that switches thousands of Ampere have to run at lower resonant frequencies.
If we have a CM300 DRSSTC running at a resonant frequency of 100 kHz and switching 1000 A the rate of change of current would be:
A CM300DY-24H IGBT have a total of 700 ns (Toff and Tfall) time, dividing by 4 gives us 175 ns, so switching off will begin as the collector current is still at 110 A.
So soft switching or zero current switching 1000 A will have less then 20% of the turn off losses seen in the datasheet for hard switching 110 A.
The same calculations and conclusion is valid for turn on losses.
Thermal impedance is a important parameter if you want to understand why we can switch currents much larger than those the IGBT bricks are designed for.
In the graphic below the red box shows the typical pulse duration in a DRSSTC, 200 us. The three lines mark from top and down what corresponds to 100 BPS, 50 BPS and last single pulse.
This is a example of a graph, it is not specific to a CM300 or CM600, it is only showing how to read out a value from a duty cycle.
D is the relative duty cycle and is calculated from full square wave period. D = t1 / t2 where t1 is the on part of the period and t2 is the off part.
So for 100 BPS:
Comparing the read out according to D = 0.02, 0.0081 K/W to the 0.17 K/W rise from a 50% duty cycle given in the datasheet example, the temperature rise at 200 us at 100 BPS DRSSTC operation is a factor 21 lower. Taking it to the extreme, at 300 BPS with D=0.064, 0.012 K/W it is a factor 11.33 lower than the 50% duty cycle. Further reduction could be made as the resonant current is swinging maybe 10 times through the 200 us on time and it is thus less than half of square wave area in terms of losses.
So a very rough estimate is that the switching losses should in best worst case scenario still be 20-40 times lower than those given for hard switching, assuming that we can cool that losses off between pulses, which we will look at next.
Fmax1 and Fmax2 switching speeds
Fmax1 is the maximum frequency rating at a very specific set of test parameters and its curves are not always to be found in datasheets, Switching speed in kHz vs. collector current. Fmax1 is only valid for low currents as it solely looks at the switching times and does not take switching losses into consideration as there are virtually no heat generated from switching very low currents. In regard to DRSSTCs, Fmax1 is of no interest to us.
Fmax2 is the maximum switching frequency calculated from the switching losses and maximum junction temperature. Fmax2 will in 99% of cases, for hard switching, result in a lower frequency than Fmax1. It can even be the other way around for DRSSTCs as we operate with very short on times.
As an example I will calculate the maximum frequencies for a Mitsubishi CM600DU-24F IGBT brick for a DRSSTC with 2000 A primary current. 200 us on time, 200 BPS, 600 VDC supply, 24 VDC gate drive, 5 Ohm gate resistors.
We want Tjunction to stay below 80ºC and have Tcase cooled to stay below 50ºC. A advisable rule is to keep the temperature ripple below 30ºC, we often use second hand IGBT bricks and we do not know their usage history. To avoid real fast degeneration of die and bonding wires inside the IGBT, we will aim to reduce large temperature swings.
It is given by Microsemi  that for hard switching all the switching times should not last longer than 5% of the on time. Since soft switching have under 20% of the losses as we discovered earlier, we will be bold and calculate with 10% duty cycle. We will also assume the on/off switching times to be 4 times faster due to resonant switching, as described earlier.
Plotting in the numbers gives us the following.
The thermal limit to frequency is derived from the power dissipation formula which is based on conduction losses, switching losses and the time required to dissipate those losses.
The higher the conduction loss, the more time is required to dissipate the switching losses. So the inverse of tdiss is the maximum frequency. RθJC is the junction to case thermal resistance, Tj is the temperature of the junction and TC is the temperature of the case.
By extrapolation of the output characteristics performance curves, we get VCE(sat) is approximately 4V at 2000A and Tjunction 80ºC.
Our duty cycle is derived from 200 us on time and 200 BPS with corresponds to 4%. It is already a very low loss despite that we calculate it for a square wave and not the actual number of primary cycles we have in a DRSSTC burst, to account for the ringing sinusoidal current waveform we could assume the duty cycle to be at least half of the above, so we continue with 0.02 duty cycle.
RθJC is in the case of the CM600 given as 0.081 K/W, but we also have to look at the transient thermal impedance characteristics, as these presented as a normalized transient thermal impedance Zth(JC). The steady state thermal impedance given as RθJC have to be multiplied by the factor gotten from the normalized graph according to the duty-cycle. At 0.02 we are as close to factor 1, so I will proceed with 0.081 K/W. It is worth noting that this is a worst case value where case temperature is not measured directly under the chip, if we used that value we could use the lower 0.032 K/W.
Total power that can be dissipated within our temperature limit is
To find the switching losses, we have to estimate the change of current rate from the frequency that we would like to design the DRSSTC for.
For a CM600DU-24H it is given that Toff and Tfall is 1100 ns in total, 275 ns when assumed 4 times faster, so switching off will begin as the collector current is still at 138 A. Ton and Trise are 650 ns in total, 167 ns when assumed 4 times faster, so switching on will begin as the collector current is still at 83 A. We can now find the switching losses from the energy loss curves, find the energy values for 138 A off and 83 A on and divide the read out value by 10 to derate for the exponential decay of the current wave form.
So we can read out that Eon is 5 mJ, Eoff is 25 mJ and we take 20% of the on / off loss to account for soft switching and the difference in rise and fall curves as seen earlier. As the datasheet example above is given at 15 V gate drive, we can only assume the losses to be less as we drive the gates harder at 24 V.
We can now calculate our thermally limited switching speed for 2000 A and temperature limits.
Just because the junction can withstand this switching speed when the switching losses are used in the calculation, it does not mean that we can actually drive the IGBT at this speed with a regular DRSSTC universal driver. It is however a important check to see if we can run seemingly slow bricks at higher speeds than what could be expected in a hard switching application.
Terminal current limitation
In datasheets for newer IGBTs, like the Mitsubishi 6th generation bricks like CM400, CM800 and CM1000 there is a star note to the collector current.
“DC current rating is limited by power terminals”
A DRSSTC does not operate at DC, but we operate them at far higher pulse currents, so we do have a similar problem with heating of the connections. The terminals could be made from thinner copper than earlier models and thus there is now a warning against current limitations in the power terminals. If new IGBTs are used, it could be a good idea to construct the busbar in such a way that it can dissipate as much heat from the IGBT terminals as possible.
If we want to switch currents larger than the pulse current specifications, we can take advantage of driving the gate harder by applying a voltage 20% higher than the rating. It is normal to drive a 20V rated gate by 24V.
Collector-Emitter voltage VCES should be kept at a maximum of 400V for 600V devices and 800V for 1200V devices.
Collector-Emitter On/Saturation voltage VCE(sat) should be as low as possible. Somewhere between 2 to 3 V given in the datasheet example should still be good when extrapolated for our high peak current.
The temperature ripple between junction and case should be kept at a maximum of 30ºC.
We have seen that datasheet where only information for inductive hard switching is given, it can still be used to extrapolate data to an approximation of soft switching used in DRSSTCs.
Calculation of the Fmax2 frequency is the only way to check your IGBT against your design goals for a DRSSTC, if not just basing it on someone else’s proven design as found below in the table.
Reality have shown that it is possible to drive a CM600 brick at much higher currents and frequencies as we calculated for the Fmax2 frequency. It should however be noted that expected life time of the IGBT might be in the hundreds of hours instead of 10s of thousands, when driven so hard.
The real limitations of frequency the IGBT can be driven at will be its internal parasitic inductance and the power required to drive the gates, which will rise dramatically at high frequencies for large gate capacitance. The widely used universal driver from Steve Ward or similar is used for the coils mentioned in the following table. Driving a large brick much faster will require a much more powerful driver.
Table of PROVEN switching speeds for different IGBT switches
|Frequency||Peak current||Part number||Proven by|
|35 kHz||6000 A||Infineon FZ1200R12KL4C||zilipoper on 4hv.org|
|35 kHz||4000 A||Powerex CM600DU-24NF||zrg on 4hv.org|
|35 kHz||2000 A||CM1400DU-24NF||Adam Munich on 4hv.org|
|37 kHz||1500 A||Powerex CM600DU-24NF||Mads Barnkob|
|36 kHz||1300 A||Powerex CM300DY-24NF||Fabrício Franzoli|
|42 kHz||1300 A||SKM400GB124||Finn Hammer|
|42 kHz||1200 A||Powerex CM300DY-24||Dzejwor on 4hv.org|
|65 kHz||650 A||MBM200A6||Hydron on 4hv.org|
|70 kHz||500 A||IXYS IXGN60N60C2D1||Mads Barnkob|
|70 kHz||750 A||CM300DY-24H||Hydron on 4hv.org|
|72 kHz||700 A||CM300DU-24NFH||Gao Guangyan|
|75 kHz||490 A||BSM75GB120DN2||mmt on 4hv.org|
|75 kHz||800 A||Fairchild HGT1N40N60A4D||Steve Ward|
|80 kHz||750 A||SKM200GB125D||Hydron on 4hv.org|
|87 kHz||850 A||CM200DU-24F RTC removed||Alex Yuan|
|120 kHz||450 A||CM200DU-24F||Gao Guangyan|
|150 kHz||350 A||CM75BU-12H||Fabrício Franzoli|
|150 kHz||500 A||IXGN60N60C2D1||Alex Yuan|
|150 kHz||350 A||HGTG40N60A4D||Fabrício Franzoli|
|200 kHz||700 A||SEMIKRON SKM50GB100D||brtaman on 4hv.org|
|270 kHz||300 A||FGA60N65SMD||Alex Yuan|
|327 kHz||300 A||IXYS IXGN60N60C2D1||Mads Barnkob|
Table of FAILURE switching speeds for different IGBT switches
|Frequency||Peak current||Part number||Proven by|
|56 kHz||3500A||CM600HA-24H||Kizmo at 4hv.org|
|42 kHz||2000A / 500 BPS||SKM400GB124||Finn Hammer|
|Previous topic: Busbar and primary circuit||Next topic: DC bus capacitor|
 International Rectifier “IGBT Characteristics”, Application Note AN-983, July 2012.
 Dipl.-lng. Markus Krogemann. “The Parallel Resonant DC Link Inverter-A Soft Switching Inverter Topology with PWM Capability”, Submitted to the University of Nottingham for the degree of Doctor of Philosophy, February 1997.
 Jonathan Dodge, P.E and John Hess. “IGBT Tutorial”, Application Note APT0201 Rev. B, July 1, 2002.