Ericsson Radio Base Station RBS6000 teardown

The RBS 6201 two radio shelves can be equipped with virtually any combination of GSM, WCDMA and LTE, which are available for all common frequencies.

A single radio shelf can provide up to 3×8 GSM or 3×4 MIMO WCDMA or 3×20 MHz MIMO LTE or a combination of above standards.

The RUS supports 60 Watt output power for any standard with a bandwidth of up to 20 MHz. Each unit is capable of handling four cell carriers in both downlink and uplink. Multiple RU can be combined to create various single- or dualband configurations with 1-6 sectors and 1-4 carriers.

The RBS application software is distributed over several processors using the interprocessor communication offered by the platform. The main processors of the
RBS 6000 cooperate to form a main processor cluster (MPC) that executes most of the
control software. The processors that make up the MPC are equal in terms of control —
that is, there are no master-slave relationships between them. However, if one of the processors fails, the program execution is moved to another main processor in the
MPC. For control, most boards are equipped with a board processor (BP). Those units
that do not contain a board processor are monitored by other units.

The following 25 minute video shows the teardown step by step with explanations, high resolution pictures of content is in the last part of the video and also further down this post.

The system specific controllers are marked in the following pictures, these are handling system monitoring, telecommunication protocol decoding and encoding.

The system monitor CPU is the Ericsson ROP 101 1190/2 “AUC” which is a part of the earlier mentioned MPC. The Xilinx Virtex5 XC5VLX85T is a 550 MHz FPGA that either handles some system monitoring or the bus network interface.

The Ericsson ASIC ROP 101 089/3 “WARP 1” is at a best guess the encoding processors as they sit next to the analogue to digital converters described in the receiver part below.

The Altera Stratix III EP3SL150F780I3N is a 800 MHz FPGA that at a best guess is the decoding processor as it sit next to the digital to analogue converters described in the transmit part below.

Looking at the part of the circuit board that was marked receive in the above pictures, we can in the following pictures see the analogue signal from the diplexer is the input to the two golden connectors.

The main signal goes through the Anaren Xinger 1P603S hybrid coupler and best guess is that the phase shifted signal is distributed on to the smaller couplers and from there to the different signal monitoring parts of the circuits. The Analog Devices OP747 is a precision micro power op-amp and the Maxim MAX1154 is a 10 channel 10-bit system monitor.

The signal goes from the Anaren Xinger 1P603S to the Maxim MAX19997 Dual 2.3 – 2.7 GHz down-conversion mixer, which from the shielded Panasonic PA9F18 above it which is a ADF4153 local oscillator running at around 3 GHz, does a down-conversion from 2.6 GHz to 400 MHz according to the following formula. Intermediate frequency (400 MHz) = Local oscillator (3000 MHz) – RF signal (2600 MHz).

Sequencing and sampling is handled by the Analog devices ICs ADF4002 which is a 400 MHz bandwidth phase detector / frequency synthesizer and the AD9510 which is a 1.2 GHz clock distribution sequencer.

The signal is now split into two isolated lines through the TriQuint 856771 which is a 358.4 MHz SAW filter. SAW is short for surface acoustic wave and is basically two transducers on each their side of a piezoelectric crystal. The input transducer will make the crystal vibrate and the output transducer will generate a output from the vibrations, this is highly efficient at up to 99.99%.

The signal is fed from the SAW filters to a Skyworks SKY73084 300-500 MHz downconversion mixer which have the local oscillator right to it, but I am unsure of the frequency, but a guess is down to 20 MHz which is the advertised data bandwidth of the RBS6000 system.

Through unknown ICs and a passive filter the signal is now fed to the analogue to digital converters, the two Linear Technology LTC2208 ADC which are 16- bit and 800 MSPS. The digital data stream is now fed through the Texas Instruments LVDT386 250 MSPS differential line receivers to the Ericsson “WARP 1” encoding processors.

Looking at the part of the circuit board that was marked transmit in the first pictures, we can in the following pictures see the digital signal from the decoding processor is the input to the digital to analogue converters.

The Texas Instruments DAC5689 dual channel 800 MSPS 16-bit DAC converts the digital data stream from the Altera FPGA into a analogue signal that goes through the ST Microelectronics upconversion mixer marked 079/6 R1A BAJ HPACS Vd KOR 025, there is however no datasheet available for this IC. Neither is there for the last IC marked H305A MDB3 that sits just before the gold plated socket that goes to the power amplifier.

The following pictures shows the separate power amplifier module. It is apparent that this circuit board is made for many different layouts, frequencies or technologies from the amount of unpopulated areas on the board.

The input from the above transmit circuit on the main board comes through the input connectors to the right in these pictures. The first IC is not able to be identified but must be a preamplifier before entering the Freescale SW7IC2725GN integrated amplifier that also has no datasheet available. From here it goes through a small circulator to isolate the preamplifier from the power amplifier part.

The expanding boxes and funnel like traces are low pass filters and the many stubs and quarter circle quarter wave length traces are working as filters too, to either short or be open circuit at the RF frequency depending on them being grounded or not.

The NXP MRF7S27130HS N-channel RF MOSFET which is capable of 105 Watt CW mode at 2.6 GHz, the combination of the two outputs suggests that it is either a balanced amplifier or a Doherty amplifier setup, seen from the different lengths in the output paths.

The signal is phase shifted through the Anaren Xinger II XC2100-30S hybrid coupler and the isolation between antenna connector and power amplifier is done by the circulator. A signal entering on port 1 of a circulator can only exit on port 2, a signal entering from the antenna on port 2 can only exit on port 3 into the attenuation resistor that goes to ground. This is to prevent signals from going backwards into the amplifier.

About Mads Barnkob

Electrician, experimenter and amateur scientist with experience in industry automation, programming and all kinds of high voltage generating electronics.
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