The RBS3206 macro is an indoor Radio Base Station with one to four carriers and one to six sectors at 20/40 Watt RF output power per carrier.
All the boards that I have comes from the middle row in the above picture and unfortunately I did not have any of the diplexers at the top or the power supplies that are at the bottom row.
The following 24 minute video shows the teardown step by step with explanations, high resolution pictures of the boards is in the last part of the video and also further down this post.
In 1999 Ericsson had 17 test systems running around the world with WCDMA, which is better known as 3G among normal people. WCDMA stands for Wideband code-division multiple access. This RBS3206 indoor macro system is from around 2008. It also supports all these technologies GSM / EDGE, WCDMA / HSPA and LTE.
The RBS application software is distributed over several processors using the interprocessor communication offered by the platform. The main processors of the
RBS 3000 cooperate to form a main processor cluster (MPC) that executes most of the
control software. The processors that make up the MPC are equal in terms of control —
that is, there are no master-slave relationships between them. However, if one of the processors fails, the program execution is moved to another main processor in the
MPC. For control, most boards are equipped with a board processor (BP). Those units
that do not contain a board processor are monitored by other units.
The circuit analysis was made rather difficult from all the custom marked Ericsson parts and other ICs where it is not possible to locate a datasheet.
The main CPU is a Ericsson “AUC” with part number ROP 101 1190/2 which has 128MB ISSI42S32400B SDRAM and application is stored in Intel Numonyx 128MB flash memory.
The Altera HardCopy II is a 350 MHz ASIC with 8847360 RAM bits that handles the translation of the telecom data protocol to a single bit data stream that is sent to the digital to analog converters in the transmit part of the board.
The Ericsson “WARP 1” ASIC labelled ROP 101 089/1 R1A is the encoding IC that takes the single digital data stream from the analog to digital converter and encodes it back into the telecom protocol to go back on the wired network.
The two connectors, that can barely be seen in the top of the picture, is the connections to the receiving part of the diplexer module.
The signal first passes through the 3rd order ceramic resonator bandpass filters and goes to the first Maxim MAX9993E down conversion mixers that brings the 1950 MHz signal down to a frequency between 40 to 350 MHz, by the use of the Analog Devices ADF4106 6 GHz local oscillators for the intermediate frequency.
A TriQuint SAWTEK 856496 208 MHz SAW filter, which is a sonic acoustic filter, insures a high efficiency isolation between first and second down conversion mixer setup.
The second Infineon 60744E, which is a unknown IC, down conversion mixer brings the signal even further down in carrier frequency by the use of the Analog Devices ADF4116 550 MHz local oscillator for the intermediate frequency.
At last the analog signals are converted into two channels of fast single digit data lines by the Analog Devices AD80137 which is a ADC with unknown specifications.
The input to the 3G / WCDMA part of the receiving circuitry goes directly to the circulator at the power amplifier board. I am not sure how this work, if it is just for internal measurements of the amplified signal or if it is a part of the cell network.
The signal goes through the Maxim MAX9996 down conversion mixer which changes the signal to a lower frequency with the use of the Analog Devices ADF4106 6 GHz local oscillator for the intermediate frequency.
At last the analog signal is converted to a digital data stream by the Analog Devices AD9233 ADC which has a 125 MSPS bandwidth at 12-bit resolution. This data is sent to the Ericsson “WARP 1” ASIC described above.
The Altera HardCopy II described above delivers the single digital datastream to the two Texas Instrument DAC5687 which are 500 MSPS bandwidth with 16-bit resolution digital to analog converters.
The clocking and timing of signals are controlled by several oscillators and crystals (Toyocom 491.54 MHz and Analog Devices ADF4001 200 MHz clock generator) around the DACs and a Analog Devices AD9510 1.2 GHz clock distribution IC handles the overall task of this.
The upconversion mixer ICs IRF370333 are unknown and uses the also unknown local GHz oscillator seen in the lower left of the picture.
The signal from the above described transmitting part of the main board comes into the two connectors in the upper left corner. From here it runs through 3 Xinger JP503S hybrid couplers for various phase shifting of the signal.
The pre-amplifiers are Freescale SW4IC2230GNB which are unknown, but a qualified guess would be that 4 is for 40 Watt and 2230 is for 2230 MHz, so it is rated somewhere along those lines.
The Infineon PTFA211801E high power RF LDMOSFETs handles the power amplification with their 180 Watt rating at 2110 to 2170 MHz.
The combined outputs run through the Xinger II XC2100A-30S hybrid coupler before entering the output circulator that ensures that the signal from port 1 exits at port 2 and any reflected energy from the antenna output on port 2 is absorbed by the 50 Ohm termination at port 3.