The RBS 3202 macro is an indoor Radio Base Station with one to four carriers and one to six sectors at 20/40 Watt RF output power per carrier.
All the boards that I have comes from the middle row in the above picture and unfortunately I did not have any of the power amplifiers that are all at the bottom row.
In 1999 Ericsson had 17 test systems running around the world with WCDMA, which is better known as 3G among normal people. WCDMA stands for Wideband code-division multiple access. This RBS3202 indoor macro system is from around 2008. It also supports all these technologies GSM / EDGE, WCDMA / HSPA and LTE.
The RBS application software is distributed over several processors using the interprocessor communication offered by the platform. The main processors of the
RBS 3000 cooperate to form a main processor cluster (MPC) that executes most of the
control software. The processors that make up the MPC are equal in terms of control —
that is, there are no master-slave relationships between them. However, if one of the processors fails, the program execution is moved to another main processor in the
MPC. For control, most boards are equipped with a board processor (BP). Those units
that do not contain a board processor are monitored by other units.
The following 18 minute video shows the teardown step by step with explanations, high resolution pictures of content is in the last part of the video and also further down this post.
The circuit analysis was made rather difficult from all the custom marked Ericsson parts and other ICs where it is not possible to locate a datasheet.
In the above pictures we see the first system controller board which has the primary power supply input and splits it into multiply supply voltages that goes to the back plane and supply power to the rest of the modules. The bus connections are handled by a Lattice ispGDX2 fast serial I/O IC, it is a high bandwidth BUS interface that can run at speeds up to 38 Gbps.
The main CPU seems to be the Philips VP22530B3 with the Ericsson part number ROP 101 728/2, as this is the CPU that stands out from the identical processors on all the boards that are part of the MPC mentioned first in the article.
The board processor is a Ericsson “DBC” with part number ROP 101 1175/4 which has two Samsung K4S641632K RAM chips next to it, which are each 64MB RAM.
In the above pictures we see the second system controller board which at my best guess just do surveillance of the system. It has 3 identical Ericsson “SPUTNIK” ICs with the part number ROP 101 015/1 that connect to 9 high speed serial lines that goes to the back plane.
The board processor is a Ericsson “DBC” with part number ROP 101 1175/1 which has two ISSI IS42S16400B RAM chips next to it, which are each 64MB RAM.
The above pictures makes me believe that the pre-amplifier board is more of a DAC with filters that an actual amplifier. So I think this is just used for translation of the telecommunication protocols to analogue signal that can be fed to the power amplifier that we could see at the bottom of the system overview picture at the top of the article.
The large Ericsson CPU with part number ROP 101 10125/2 must be handling the protocol translation and feeds high speed digital data to the boards DACs, which are impossible to identify due to custom part numbers and such.
The only identifiable IC is a ADC, a Analog Devices AD9238B which is a 12 bit ADC that has dual channels with each a speed of 65 MSPS.
The board processor is a Ericsson “DBC” with part number ROP 101 1175/1 which has two Samsung K4S281632K RAM chips next to it, which are each 128MB RAM.
The analogue receiver output card that connects directly to the diplexer via a large pin header has a power supply part which seem to feed the diplexer board too. The different outputs at the left top are all split in A and B channel, from the hybrid coupler that gives a phase shifted signal and from the traces it can be seen splitting out.
The board processor is a Ericsson “DBC” with part number ROP 101 1175/3 which has two ISSI IS42S16400B RAM chips next to it, which are each 64MB RAM.
That board also have a first generation Altera Cyclone FPGA that maybe has to do with the connectors in the upper right corner near all the PCB cut-outs and the blue 50 Ohm termination to ground.
The diplexer top cover board also have a first generation Altera Cyclone FPGA in the lower left corner. At the top we can see the two monitor outputs and at the back of the diplexer are the transmitter inputs, these would connect to the power amplifiers sitting at the bottom of the cabinet.
The up side down L shaped cut-outs are the connectors from the diplexer tuned cavities to the antenna connector at the front. The two smaller clusters of SMD components that are on a slightly lighter colour of blue are receiving amplifiers that connect back to the back plane RF connectors and properly back to the pre-amplifier board for analogue to digital conversion.
It is worth noting that these two circuits are not identical, which can be seen in the close up pictures of each. It can also be seen how the signal is led from the circuits to the back plane by ground stitching that runs through and break some other stitching patterns.
The diplexer itself is a little unusual by having a printed circuit board as the top cover and from that design could only have the adjust pins from the back side going up through the columns and not as in many many other designs where the pins goes through the cover and down near the columns in the tuned cavities.